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Course Learning Outcomes:

1. Understand quantitative design and analysis of computing systems, as well as the instruction set architecture design for RISC architectures.
2. Describe the concepts of hierarchical memory subsystems, including multi-level caches, advanced optimization techniques and integration with pipelined processors, as well as virtual memory.
3. Understand design trade-offs in processor design including pipelined processors, in-order vs. out-of-order execution, branch prediction techniques, different cache and TLB organizations, and through simulation.
4. Describe software multithreading and multicore computing by writing parallel programs using shared-memory and message-passing programming models.
5. Analyze/design single-issue pipelined datapath and control unit, realize how structural, data and control hazards can affect performance, and how they can be handled statically or dynamically at runtime.
6. Analyze/design advanced instruction level parallelism (ILP), including multiple-issue pipelined processors with static scheduling (VLIW), dynamic scheduling and speculation (superscalar), and hardware multithreading.
7. Analyze/design multicore architectures and shared memory multiprocessors with a focus on thread level parallelism (TLP) and snooping and directory-based cache coherency protocols; as well as data- level parallelism (DLP) and GPU architectures.